Glitch Analysis and Reduction in Digital Circuits

Static Simulation of CNTFET-based Digital Circuits

   In this paper we implement a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits. To verify the validity of the obtained results, they are compared with those of Wong model, resulting in good agreement, but obtaining a lighter ensuring compile and shorter execution time, which are the main character...

Digital Circuits Delay Analysis

The speed of digital circuit is one of the most restricting factors in the deep sub-micron and multigigahertz integrated circuits design. It is directly dependent on the circuit delay. Scaling down the technologies and increasing the operational frequency make the delay problems more important. This paper studies the delay in digital circuits, starting from the design process, scaling down the ...

Energy Reduction and Fundamental Energy Limits in Digital VLSI Circuits

A Glitch in the Theory of Delay - Insensitive Circuits

There is a questionable assumption made in the theory and practice of delay-insensitive circuits, as presented by Dill Dil88b] and Burns and Martin BM88]. The problem is illustrated by the following puzzle. Puzzle: Consider an OR gate (see Figure 1) with inputs labeled a and b, and an output labeled c. Suppose that the circuit initially has a = 1, b = 0 and c = 1; The b input then rises, and th...

A Review on Glitch Reduction Techniques

This paper presents different techniques for reducing glitch power in digital circuits. The aim of this study is to minimize glitch power as glitch power comes under dynamic power, so that power dissipation will reduce up to some extent in digital circuits. Warren Shum et.al [2011] work shows glitch power in FPGA’s varies from 4 % to 73 % of total dynamic power having an average of 22.6 %. Warr...